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逻辑设计是计算机科学、计算机工程和电气工程等专业的理论基础。学好逻辑设计需要三个环节：理论知识、习题和实验。因此，本书在强调基础知识的同时，结合着大量实例进行讲授，并给出了大量例题，同时还附有大量习题和每章的测验题。此外，还安排有4个实验操作平台和26个实验，以便把理论和实践紧密联系起来。
本书是计算机、电气工程和通信、电子等专业的学生学习逻辑设计的教材，同时也是相关专业工程技术人员的参考用书。

Preface
Chapter Introduction
1.1 A Brief Review of Number Systems
1.2 The Design Process for Combinational Systems
1.3 Don’t Care Conditions
1.4 The Development of Truth Tables
1.5 The Laboratory
1.6 Solved Problems
1.7 Exercises
1.8 Chapter 1 Test
Chapter 2 Switching Algebra and Logic Circuits
　2.1 Definition of Switching Algebra
　2.2 Basic Properties of Switching Algebra
　2.3 Manipulation of Algebraic Functions
　2.4 Implementation of Functions with AND, OR, and NOT Gates
　2.5 From the Truth Table to Algebraic Expressions
　2.6 Introduction to the Karnaugh Map
　2.7 The Complement and Product of Sums
　2.8 NAND, NOR, and Exclusive-OR Gates
　2.9 Simplification of Algebraic Expressions
　2.10 Manipulation of Algebraic Functions and NAND Gate Implementations
　2.11 A More General Boolean Algebra
　2.12 Solved Problems
　2.13 Exercises
　2.14 Chapter 2 Test
Chapter 3 The Karnaugh Map
　3.1 Minimum Sum of Product Expressions Using the Karnaugh Map
　3.2 Don’t Cares
　3.3 Product of Sums
　3.4 Minimum Cost Gate Implementations
　3.5 Five- and Six-Variable Maps
　3.6 Multiple Output Problems
　3.7 Solved Problems
　3.8 Exercises
　3.9 Chapter 3 Test
Chapter 4 Function Minimization Algorithms
　4.1 Quine-McCluskey Method for One Output
　4.2 Iterated Consensus for One Output
　4.3 Prime Implicant Tables for One Output
　4.4 Quine-McCluskey for Multiple Output Problems
　4.5 Iterated Consensus for Multiple Output Problems
　4.6 Prime Implicant Tables for Multiple Output Problems
　4.7 Solved Problems
　4.8 Exercises
　4.9 Chapter 4 Test
Chapter 5 Larger Combinational Systems
　5.1 Delay in Combinational Logic Circuits
　5.2 Adders and Other Arithmetic Circuits
　5.3 Decoders
　5.4 Encoders and Priority Encoders
　5.5 Multiplexers
　5.6 Three-State Gates
　5.7 Gate Arrays—ROMs, PLAs, and PALs
　5.8 Larger Examples
　5.9 Solved Problems
　5.10 Exercises
　5.11 Chapter 5 Test
Chapter 6 Analysis of Sequential Systems
　6.1 State Tables and Diagrams
　6.2 Latches and Flip Flops
　6.3 Analysis of Sequential Systems
　6.4 Solved Problems
　6.5 Exercises
　6.6 Chapter 6 Test
Chapter 7 The Design of Sequential Systems
　7.1 Flip Flop Design Techniques
　7.2 The Design of Synchronous Counters
　7.3 Design of Asynchronous Counters
　7.4 Derivation of State Tables and State Diagrams
　7.5 Solved Problems
　7.6 Exercises
　7.7 Chapter 7 Test
Chapter 8 Solving Larger Sequential Problems
　8.1 Shift Registers
　8.2 Counters
　8.3 Programmable Logic Devices (PLDs)
　8.4 Design Using ASM Diagrams
　8.5 One-Shot Encoding
　8.6 Hardware Design Languages
　8.7 More Complex Examples
　8.8 Solved Problems
　8.9 Exercises
　8.10 Chapter 8 Test
Chapter 9 Simplification of Sequential Circuits
　9.1 ATabular Method for State Reduction
　9.2 Partitions
　9.3 State Reduction Using Partitions
　9.4 Choosing a State Assignment
　9.5 Solved Problems
　9.6 Exercises
　9.7 Chapter 9 Test
Appendix A Laboratory Experiments
　A.1 Hardware Logic Lab
　A.2 WinBreadboard. and MacBreadboard
　A.3 Introduction to LogicWorks 4
　A.4 Introduction to Altera Max+plusII
　A.5 A Set of Logic Design Experiments
Appendix B Answers to Selected Exercises
Appendix C Chapter Test Answers
Index